Product Summary

The CY37128VP160-125AXC is a CMOS CPLD, whcih provides a range of high-density programmable logic solutions with unparalleled system performance. The CY37128VP160-125AXC is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block of CY37128VP160-125AXC features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs.

Parametrics

CY37128VP160-125AXC absolute maximum ratings: (1)Storage Temperature: –65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage to Ground Potential: –0.5V to +7.0V; (4)DC Voltage Applied to Outputs in High-Z State: –0.5V to +7.0V; (5)DC Input Voltage: –0.5V to +7.0V; (6)DC Program Voltage: 4.5 to 5.5V; (7)Current into Outputs: 16 mA; (8)Static Discharge Voltage > 2001V; (9)Latch-up Current > 200 mA.

Features

CY37128VP160-125AXC features: (1)In-System Reprogrammable (ISR CMOS CPLDs: JTAG interface for reconfigurability, design changes do not cause pinout changes, design changes do not cause timing changes; (2)High density: 32 to 512 macrocells, 32 to 264 I/O pins, five dedicated inputs including four clock pins; (3)Simple timing model: no fanout delays, no expander delays, no dedicated vs. I/O pin delays.

Diagrams

CY37128VP160-125AXC block diagram

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